Current feedback multivibrator utilizing transistors



. I CURRENT FEEDBACK MULTIVIBRATOR UTILIZING TRANSISTORS 2 Sheets-Sheet2 Filed Aug. 9, 1955 Ru us m 5 M p W a Qu m m W u w 7% wwQ M -A 8a m w93w Q. 2 \H A a w Q Q Q R United States Patent CURRENT FEEDBACKMULTIVIBRATOR UTILIZING TRANSISTORS Cravens L. Wanlass, Whittier,Calif., assignor, by mesne assignments, to Thompson Ramo WooldridgeInc., Cleveland, Ohio, a corporation of Ohio Application August 9, 1955,Serial No. 527,191

'5 Claims. (Cl. 307-885) This invention relates to a current feedbackflip-flop utilizing transistors and, more particularly, to acircuit ofthis type wherein high stability is achieved, in addition to high-speedtrigger response, improved pulse sensitivity, and improvedpower-supplying capacity.

In most of the previously devised transistor flip-flop 2,916,636Patented Dec. 8, 1959 ICC state conditions. The effect of the limitationupon stability may also be recognized by noting that where the circuits,or so-called bistable multivibrator circuits, the

two-state characteristic of the circuit is achieved by operating thetransistors in their negative resistance regions of conductance. This isachieved in the case of a pointcontact transistor by connecting arelatively high impedance in series with the base of the transistor,resulting in a regeneration effect. Thus typically the applicablepatents in this field show the negative resistance characteristic as,for example, is done in Figs. 2, 3; 2, 6; 2, 5; 3-6, shown respectivelyin Patents 2,579,336 to A. J.

Rack; 2,614,140 to J. G. Kreer, Jr.; 2,614,142 to J. o.

additional circuits in order to obtain the complement of a signal as maybe obtained through the cross-coupled amplifier type of circuit. Thismeans, therefore, that any theoretical advantage in simplicity in thesingle transistor flip-flop is lost Where complementary signals arerequired.

Trigger circuits utilizing this negative resistance function are highlysensitive to changes in circuit parameters and the above-describedpatents are primarily concerned with improved arrangements for makingthe circuits less sensitive to such parameter changes.

However, the op- I v eration of even these improved circuits has stillproved to be somewhat marginal and reliability is achieved only at theexpense of rather complicated circuit arrangements.

A further limitation inherent in the conventional technique is theemployment of voltage feedback where a I relatively low impedance sourcepoint on each ofthe transistors is utilized to control the condition ofthe other transistor through a high impedance input circuit. Ef-

fectively, the conventional voltage feedback technique is a directequivalent of the well-known Eccles-Jordan trigger circuit employingvacuum tubes where the anode circuit of each vacuum tube provides a lowimpedance source which is coupled to the high impedance grid controlcircuit of the other tube. 1 1

It will be shown herein in the detailed description which follows thatthe voltage feedback technique is inherenfly self-limiting with respectto the range of voltage changes which may be allowed between the twostable states. As a result the stability of the voltage feedbackarrangement is greatly limited since such stability is a voltage changebetween two states is small, noise or other transient signals may reachthe voltage difference level and cause spurious triggering of thecircuit.

Furthermore, the conventional bistable circuit arrangement has limitedutility with respect to the amount of load current or power it cansupply. One reason for this is that in a voltage feedback arrangement aheavy load may reduce the voltage difference between the two stablestate conditions so that at best the circuit becomes unreliable inoperation if not completely unstable.

In addition to this, the fact that the voltage feedback" arrangementspecifies a high input impedance controlcircuit means that the frequencyresponse or pulse'triggering range is somewhat limited.

The present invention obviates these and other disadvantages which areinherent in the prior art by providing a transistor flip-flop wherein atwo-state current characteristic is achieved through a current feedbackarrangement where the difierence in current conduction states may varyin the order of 10 to 1, as compared to a typical voltage feedbackarrangement which may provide a voltage variation of 10 to 1. Thecurrent feedback technique, furthermore, allows a low impedance inputcircuit with the result that the flip-flop has a rapid pulse response,and at the same time allows a high trigger sensitivity. I

The invention thus allows true current triggering for a transistorflip-flop. In addition, since stability is achieved without a commonemitter biasing arrangement such as is found in the patent to Andersonet al. mentioned above, it is also unnecessary to utilize a largevoltage pulse. Thus the speed of operationis enhanced by avoiding theeffects of distributed capacity.

In its general circuit configuration the invention comprises twotransistors of opposite conductivity type (i.e. one is NPN and the otherPNP). The collector of each transistor is connected to the base of theother providing a series current feedback arrangement. Each collector isprovided with a load impedance of relatively high value, whereas eachemitter is provided with a load impedance of relatively low value;ensuring a stable arrangement where the highly conducting condition ofone transistor results in the forward biasing and highly conductingcondition of the other transistor. The collector to emitter loadimpedance ratio is made large to provide a stability safety factor.

Trigger signals then are applied to one of the base-tocollectorjunctions between the transistors and across the corresponding collectorload resistor, signals of one polarity being effective to drive thecircuit into a high con- 'duction state and signals of the oppositepolarity being effective to cut off conduction and leave the circuit ina low conduction state.

An interesting and important distinction to be noted between the currentfeedback flip-flop of the present invention and the voltage feedbackflip-flop, which is common in the art is that in one state the currentfeedback flip-flop exhibits high conduction in both transistors and inthe other in neither of the transistors; whereas in the voltage feedbackflip-flop the transistors are always in opposite states of conductivity.

Accordingly, it is an object of the present invention to provide atransistor flip-flop circuit having a high degree of current stability.

Another object of the inventionis to provide a transistor triggercircuit having high pulse sensitivity.

A further object is to provide a transistor fiip flop having a fastacting pulse response.

Yet a further object is to provide a flip-flop employing transistorsarranged in a current feedback circuit where 3 stability is achievedwithout the necessity of utilizing the negative resistancecharacteristic of the transistors, thereby obviating the necessity ofaccurately regulating the circuit parameters. p p

Still a further object is to provide a highly stable current feedbackflip-flop which is relatively insensitive to circuit parameter changeswhile at the same time being highly sensitive to trigger pulses.

A more specific object is to provide a current feedback transistorcircuit having high stability, pulse sensitivity, a low pulse responsetime, and the ability to provide a high load current.

. Another specific object of the invention is to provide a currentfeedback transistor flip-flop wherein two transistors are employedhaving their collectors and bases cross-coupled, one base-collectorjunction receiving trigger input signals; the emitter of each transistorthen including a relatively low impedanceload resistor and the collectorthereof including a relatively high impedance load resistor.

The novel features which are believed to be characteristic of theinvention, both as to its organization and method of operation, togetherwith further objects and advantages thereof, will be better understoodfrom the following description considered in connection with theaccompanying drawings. It is to be expressly understood, however, thatthe drawings are for the purpose of illustration and description only,and are not intended as a definition of the limits of the invention.

Fig. l is a block diagram illustrating the general form of theinvention;

Figs. 2a and 2b illustrate two species of the invention indicating theassociation therewith of output storage circuits;

Fig. 3 is a schematic diagram of a double current-feedback transistorflip-flop allowing an improvement in trigger pulse sensitivity; and

' Fig. 4 is a schematic diagram of a shifting register em- .ploying twoflip-flops of the type shown in Fig. 3.

Reference is now made to Fig. 1 wherein the general arrangement of thepresent invention is shown in block diagram form. As indicated in Fig. 1a current feedback multivibrator is provided wherein transistors T1 andT2 of opposite conductivity type are connected in current series, wherethe base electrode of T1 is connected to collector electrode of T2 andthe base electrode of T2 is connected to the collector electrode of T1.H The emitter electrode of T1 receives a source potential E through anemitter impedance 22;, and the emitter .electrode of T2 receives areference potential Er through an impedance Ze A collector impedance Zcis provided for T and receives a reference potential Er and, in asimilar manner, a collector impedance Zc is coupled to the collector oftransistor T and receives a source potential E Stability considerationswhich will be discussed further below dictate that the load impedancesbe defined by the inequality function: Ze Zc and Ze Zc When theoperation of the circuit is considered it will be apparent that theserelationships ensure a feedback current gain so that the circuit will bestabilized in either a highly conducting state where both of transistorsT and T 2 are conducting, or a lowly conducting state where both of thetransistors are substantially cut off.

The reference potentials are selected so that E is sufficiently greaterthan Er to forward bias transistor T during the conducting state of thecircuit and potential E is sufiiciently greater than potential Er toforward bias transistor T When silicon transistors are employed,

potential E may be equal to E and potential Er may be equal-to Ertypical values being fifteen volts for E and-B and ground potential forEr and Er However, when germanium transistors are employed, it may benecessary to back bias the transistors slightly to maintain theflip-flop circuit in the non-conducting state. In this i 4 case,potential E is made to be greater than E to backbias transistor T duringits non-conducting state and potential Er is selected to be greater thanpotential En.-

As indicated in Fig. 1 two basic input circuit possibil ities arepresent, namely an input circuit I providing an actuating signal fortransistor T being coupled to the base thereof; and an input circuit lcoupled to the base of transistor T where transistor T is a PNP asillustrated it may be triggered into conduction by the application of anegative pulse to the base or may be cut off from conduction byapplication of a positive pulse thereto. In a similar manner where T isan NPN transistor the application of a positive pulse to the base willdrive the circuit into high conduction whereas the application of anegative pulse tends to cut off T As also indicated in Fig. 1 two basicpossibilities of output circuits are possible. In one case an outputcircuit 0 is coupled to the emitter electrode of transistor T at whichpoint a relatively low impedance driving source: is available. Or anoutput circuit 0 may be coupled to the emitter of transistor T alsoproviding a low impedance driving source.

The invention may be best understood by considering the few specificexamples below, where'also the operation will be considered in furtherdetail. Reference therefore is made to Fig. 2a. Referring now to Fig. 2ait is noted that impedances Ze and Ze appear in the form of resistors Reand Re respectively. In a similar manner resistors R0 and R0 areutilized as corresponding collector impedances. Transistors T and Tagain are illustrated as of the PNP and NPN types, respectively, and areconnected as before with the base electrode of each connected to thecollector electrode of the other.

Additional circuitry is also illustrated in Fig. 2a for providing anoutput signal which may be utilized to drive a gating matrix. The outputcircuit is shown in the form of circuit 0 and includes .a capacitor C0connected inparallel to emitter resistor Re In addition a furthertransistor is required to discharge capacitor Co, as will be describedbelow.

An output signal clamping diode D0 is included for providing a lowimpedance charging source .for capacitor C0 when the collector potentialof transistor T falls below the potential E3 applied to the anode ofdiode Do. It will also be noted that two input diodes are shown forapplying positive pulses to trigger the circuit. A first input diode Dpasses positive pulses through to the base electrode of transistor Tdriving this transistor into conduction, and a second input diode D isadapted to pass positive pulses to the base electrode of transistor Ttending to cut this transistor. oil.

In order to illustrate the operation it will be assumed that transistorsT and T are non-conducting and transistor T provides a low impedancedischarging path for output capacitor C0. .If .a positivepulse then isapplied to diode D it passes 'therethrough andacross collector impedanceR0 and'drives transistor T into a conducting state. This results in thelowering of the potential at the collector electrode of transistor T dueto the drop across collector resistor Rc This lowered potential resultsin the forward biasing of transistor T and the increased conductancetherethrough. The feedback process is then completed when the increasedconduction of transistor T raises the potential across its collectorresistorRc which causes further conduction through'transistor T Thus theapplication of a positive pulse through diode D causes both transistorsT and T to sistor RC2. 'the collector resistors for T and T are combinedin a through transistor T and diode D tothe supply voltage The flip-flopmay then be triggered to the previous state by either applying anegative pulse to the base of transistor T or a positive pulse asindicated through diode D to the base of transistor T This then reducesthe conduction through transistor T and'thus ,the voltage across R0 withthe result that conduction is reduced through transistor T and thefeedback process then con: tinues in the reverse direction. Whentransistor T is cut oil transistor T provides a low impedance dischargepath for capacitor Co as pointed out above.

A circuit similar to that shown in Fig. 2a but utilizing transistors ofoppositive conductivity type is shown in Fig. 2b. Hereby way ofillustration it is assumed that transistors T and T are NPN and PNPtypes, respectively, and are turned on due to the application of anegative pulse through an input diode D coupled to the base of PNPtransistor T In a similar manner anegative pulse applied to the base oftransistor T tendsto cut it off and therefore return the circuit to itsother state. In other respects the circuit is similar to that of Fig.211 although when transistors T and T are driven into a high conductionstate capacitor C0 is discharged towards a minus potential, thedischarging rate being accelerated through diode D0 when the voltageacross R0 reaches E3. In other respects the operation of the circuit issimilar to that discussed above.

Both of the circuits shown in Figs. 2a and 2b are somewhat limited intheir speed of operation due to the fact that it is necessary to triggerthe circuit by cutting off either of transistors T or T In this case thefeedback is less active than it is when the transistors are turned on.It is possible, however, to make both triggering on and off active byelfectively combining the two types of current feedback flip-flops shownin Figs. 2a and 2b. This results in the arrangement of Fig. 3.

In Fig. 3 effectively the upper half of the circuit is similar to Fig.2a and comprises a PNP transistor T and an NPN transistor T arrangedwith the base electrode of each connected to the collector electrode ofthe other. As before resistors Reg and R0 are employed, and a diode D0is employed to apply the potential +E3 to the junction of R0 and thecollector electrode of T Furthermore, output capacitor C0 is connectedto the emitter junction of transistors T and T In a similar manner thebottom portion of the arrangement is similar to the circuit of Fig. 2bwhere transistors T and T correspond respectively to transistors T and Tof Fig. 2b. Emitter resistor Re. corresponds to resistor R2 andcollector resistor R0 corresponds to re- The important distinction tonote is that common resistor referred to as Rel-4, and the emitterresistors for T and T are combined in a common resistor referenced as ReIn the operation of the embodiment of Fig. 3 either the upper currentfeedback loop is turned on and the lower fe dback is turned off, or thereverse situation occurs. Thus when a positive pulse is applied to inputdiode D, to the base electrode of transistor T it is driven intoconduction and transistor T is also driven into conduction completingthe current feedback loop therein as indicated by the arrow. This cutsoff transistor T and transistor T In a similar manner the negative pulseapplication through input diode D drives transistor T into conductionwhich in turn turns on transistor T completing the lower feedback loopand cutting 01f transistors T and T Optional input points are shown inFig. 3 through positive pulse passing diode D which will drivetransistor T into conduction, actuating the lower feedback intoconduction loop; and a negative pulse passing input diode D for passingpulses to the base electrode of transistor T actuating the upperfeedback loop into conduction.

. 6 The circuit arrangement of Fig. 3 is illustrated in a prac-' ticalapplication in Fig. 4, where it will also 'be noted that suitablecircuit values therefor are shown. It should be noted, thatalltransi'stor and diode types indicated are specified by either theTexas Instrument Company or v General Electric. Referring now to Fig. 4i t will be noted that two feedback transistor flip-flop: stages areshown, namely F and F These stages are coupled by a diode gating circuitto be described which provides positive and negative input pulses forstage Fg'when the output signal of stage F is high and low,-respectively. These-signalsthen are applied to the junction of TexasInstruments NPN typetransistor 904, corresponding to transistor T inFig. 3,- and General Electrictransis'tor 2N43 corresponding to T -ofFig. 3. Thus when transistor stage F is in a high state, an outputcapacitor C0 (.0048 microfarad in Fig. 4) is chargedto the high level,gating diode G is backbiased so that positive clock pulse C(+) may riseto its high level and pass through'gating diode G and through an inputresistor (2K ohms) to the input circuit of flip-flop F In a similarmanner input signals. may be' entered into flip-flop stage F throughgating circuit 10. h

From 'the foregoing description it is apparent that the present,invention provides a transistor flip-flop utilizing current feedbacktoachieve a high degree of current stability. It should now be apparentthat the arrangement provided does not require the utilization of thehighly sensitive negative resistance characteristic of the transistorsand consequently is relatively insensitive to circuit parameter changes.

At the same time the circuit provided is highly sensitive to triggerpulses and provides a high stability while at the same time having arelatively good ability to provide a high load current.

While the invention has been illustrated in but a few forms, it will beunderstood that the basic concept of current feedback and stabilizationthrough the proper selection of the emitter and collector biasingimpedances may be found in a multitude of other forms. Thus it isrecognized that those skilled in the art will devise many othervariations without departing from the spirit of the present invention.

What is claimed as new, is:

1. A transistor flip-flop circuit including first and second pairs oftransistors, said transistors having base, collector, and emitterelectrodes, each pair including an NPN transistor and a PNP transistor,the base electrode of each transistor in a pair being coupled to thecollector electrode of the other transistor in the pair; emitterimpedances coupled to the emitter electrodes of the PNP transistor ofsaid first pair and the NPN transistor of said second pair,respectively; collector impedances coupled to the collector electrodesof the NPN transistor of said first pair and the PNP transistor of saidsecond pair, respectively; a common collector impedance coupled to thejunction of the collector electrodes of the PNP transistor in said firstpair and the NPN transistor in said second pair; and a common emitterimpedance coupled to the junction of the emitter electrodes of the NPNtransistor in said first pair and the PNP transistor in said secondpair.

2. The transistor trigger circuit defined in claim 1 wherein there isfurther included an input circuit for applying pulses to the junction ofsaid common collector impedance and the collector electrodes of said PNPtransistor in said first pair and the NPN transistor in said secondpair, said input circuit being responsive to negative input signals fordriving said first pair of transistors into a non-conducting state andsaid second pair of transistors into a conducting state, and beingresponsive to positive input pulses for driving said first pair oftransistors into a conducting state and said second pair of transistorsinto a non-conducting state.

3. A flip-flop circuit comprising: first and second transt r of oppositecondu t t t pe, ac av t a b se, n mit e an a l ct fir t nd. c nd m t rimpcd nc c p d to sa d emi t and fir t nd EQ Pd e t mped ces c u led. o.d p l t means f applying first and second biasing potentials to saidfirst emitter impedance and said second collector impedance e p ct ely;m ans, r app yi g first a s nd e ere P ent als t sa d firs c e t r mp ne and $2! second emitt r mp danc respec ively; d m tter im- P nces bei gof su an i y s a ls? ma nitude "the their associated collectorimpedanees and said biasing poten a s be n a e an a d reference pot ntals to fo ward bias the. e pe i e a is sters duri their con,- d v tin stte; and means c nnec in h ha of v1:91 9 id ansis qrs to he co l t 9other T e fl p-flop ci cui d fined .in c aim 3. where 9 o sai trans s ors an lPN type of transi o an the other trans sto is a N type; and wheein h e is furthe included output rc mean oup ed o t emitter electrodeof said transistor, 5 id output m a c di a t a e pac tor and 1 9141 128t a sistor of the PNP type having its emitter electrode connected to oneend of said storage capacitor and its collector electrode coupled to theother end of said storage capacitor, the base electrode of said outputtransistor being connected to the base electrode of transistor.

a transistor of theNPNtypeQthe emitter electrode of said outputtraiisistor being c oupledto one end of said storage capacitor thecollector electrode of said output transistqr vbeing coupled to theother end of said storage capacitondhe base electrode of said storagecapacitor 10 being coupled to the base electrode of said PNP transistor.

References Cited in the file of this patent UNITED STATES PATENTS2,605,306 Eberhard July 2-9, 1952 2,622,212 Anderson Dec. 16, 19522,655g609 Shockley Oct. 13, 1953 2,666,819 Raisbeck Jan. 19, 19542,673,936 Harris Mar. 30, 1954 2,770,732 Chong Nov. 13, 1956 OTHERREFERENCES Electronics, September 1953, Complementary Sym- 5 metry, byRobert D. Lohman, pages 140 to 1.43.

